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C8051F380/1/2/3/4/5/6/7/C
W E A K -P U LLU P
P U S H -P U LL
P O R T -O U T E N A B LE
VDD
VDD
(W E A K )
PORT
P O R T -O U T P U T
A nalog S elect
GND
PAD
A N A LO G IN P U T
P O R T -IN P U T
Figure 20.2. Port I/O Cell Block Diagram
20.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 20.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be
set. This applies to the VREF signal, external oscillator pins (XTAL1, XTAL2), the ADC’s external conver-
sion start signal (CNVSTR), EMIF control signals, and any selected ADC or Comparator inputs. The
PnSKIP registers may also be used to skip pins to be used as GPIO. The Crossbar skips selected pins as
if they were already assigned, and moves to the next unassigned pin. Figure 20.3 shows all the possible
pins available to each peripheral. Figure 20.4 shows an example Crossbar configuration with no Port pins
skipped. Figure 20.5 shows the same Crossbar example with pins P0.2, P0.3, and P1.0 skipped.
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when either SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART
(TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned
to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
154
Rev. 1.4
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